.*: Assembler messages:
.*: Warning: unpredictable: identical base and status registers --`sttxr w0,w1,\[x0\]'
.*: Warning: unpredictable: identical transfer and status registers --`sttxr w0,w0,\[x1\]'
.*: Warning: unpredictable: identical base and status registers --`sttxr w0,x1,\[x0\]'
.*: Warning: unpredictable: identical transfer and status registers --`sttxr w0,x0,\[x1\]'
.*: Warning: unpredictable: identical base and status registers --`stltxr w0,w1,\[x0\]'
.*: Warning: unpredictable: identical transfer and status registers --`stltxr w0,w0,\[x1\]'
.*: Warning: unpredictable: identical base and status registers --`stltxr w0,x1,\[x0\]'
.*: Warning: unpredictable: identical transfer and status registers --`stltxr w0,x0,\[x1\]'
.*: Error: reg pair must be contiguous at operand 2 -- `caspt x0,x0,x2,x3,\[x0\]'
.*: Error: reg pair must start from even reg at operand 3 -- `caspt x0,x1,x3,x4,\[x0\]'
.*: Error: operand 5 must be an address with base register \(no offset\) -- `caspt x0,x1,x2,x3,\[x0,#0x8\]'
.*: Warning: unpredictable load of register pair -- `ldtnp x0,x0,\[x0\]'
.*: Error: immediate offset out of range -512 to 504 at operand 3 -- `ldtnp x0,x1,\[x0,#508\]'
.*: Error: unexpected address writeback at operand 3 -- `ldtnp x0,x1,\[x0,#504\]!'
.*: Warning: unpredictable load of register pair -- `ldtp x0,x0,\[x1\]'
.*: Warning: unpredictable transfer with writeback -- `ldtp x0,x1,\[x0,#504\]!'
.*: Warning: unpredictable transfer with writeback -- `ldtp x0,x1,\[x0\],#504'
.*: Warning: unpredictable load of register pair -- `ldtp q0,q0,\[x1\]'
.*: Warning: unpredictable transfer with writeback -- `sttp x0,x1,\[x0,#504\]!'
.*: Warning: unpredictable transfer with writeback -- `sttp x0,x1,\[x0\],#504'
